Search - uart fpga

[VHDL-FPGA-Verilog] HCIUART

Description: 蓝牙HCI—UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
Platform: | Size: 102400 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[Com Port] use_fpga_to_design_uart

Description: 用fpga设计uart的案例,word格式-UART FPGA design with the case, word format
Platform: | Size: 130048 | Author: Terry | Hits:

[Com Port] uart_fpga

Description: 一个完全好用的程序,用ISE 8.2打开就可直接应用-A fully-to-use procedures, with ISE 8.2 can be applied directly to open
Platform: | Size: 620544 | Author: Ma liang | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: xilinx提供的verilog_uart源码,适合做串口的人学习-Xilinx provided verilog_uart source, suitable for those who study serial
Platform: | Size: 9216 | Author: 伍迪 | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: UART串行通讯FPGA实现，新手上道请多多指教-FPGA realization of UART serial communication, and newcomers on the Road, please advice
Platform: | Size: 1173504 | Author: swisky | Hits:

Description: 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
Platform: | Size: 3072 | Author: liaocongliang | Hits:

[Com Port] feng_rs0

Description: 基于FPGA的串口通信，PC给FPGA发送数据，FPGA收到数据并返回给PC-FPGA-based serial communications, PC to the FPGA to send data, FPGA Receive data and return to the PC
Platform: | Size: 305152 | Author: 王OO | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
Platform: | Size: 565248 | Author: 杨文斌 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
Platform: | Size: 280576 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] uart_receiver

Description: This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 1024 | Author: bhagwan | Hits:

[VHDL-FPGA-Verilog] uart_transmitter

Description: This UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 1024 | Author: bhagwan | Hits:

[Embeded-SCM Develop] CPLD_UART

Description: 基于FPGA CPLD设计与实现UART,一听名字就知道，不用再说了吧，-FPGA CPLD-based Design and Implementation of UART, a name, we know that you do not say any more,
Platform: | Size: 1024 | Author: 何力 | Hits:

[VHDL-FPGA-Verilog] FPGA_VHDL_code

Description: FPGA学习非常珍贵的资料，包括USB、UART、I2C、Ethernet、VGA、CAN等总线的VHDL实现，可以直接应用于实际项目中。需要的请下载。 -FPGA to learn very valuable information, including USB, UART, I2C, Ethernet, VGA, CAN bus, such as VHDL to achieve, can be directly applied to actual projects. Need to download.
Platform: | Size: 1605632 | Author: suzhenwei | Hits:

[VHDL-FPGA-Verilog] NIOS_JTAG_UART

Description: FPGA开发板上的JTAG——UART完成的工程设计，包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
Platform: | Size: 7814144 | Author: 张一 | Hits:

[VHDL-FPGA-Verilog] FPGACPLD

Description: FPGA数字电子系统设计与开发实例导航> 一书的代码，FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的，I2C,UART,USB，VGA，CAN-BUS，网络等等的书籍配套原代码。。。。使用方法： 1.拷贝到硬盘。 2.用ISE创建项目，分别加入各个代码文件，即可
Platform: | Size: 175104 | Author: bbc | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
Platform: | Size: 2048 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] Actel_Igloo_nano_UART

Description: This FPGA project include a simple version of the UART for Actel Igloo nano.
Platform: | Size: 453632 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] UART_FPGA_design

Description: FPGA通用异步收发器设计，代码均在WORD文档里，含详细说明，不错的。-UART FPGA design, the code in the WORD document, the content in detail, good.
Platform: | Size: 32768 | Author: | Hits:

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[VHDL-FPGA-Verilog] HCIUART

[VHDL-FPGA-Verilog] UART

[Com Port] use_fpga_to_design_uart

[Com Port] uart_fpga

[VHDL-FPGA-Verilog] uartverilog

[VHDL-FPGA-Verilog] uart_regs

[VHDL-FPGA-Verilog] uart

[Com Port] feng_rs0

[VHDL-FPGA-Verilog] uart8

[VHDL-FPGA-Verilog] uartfifo

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart_receiver

[VHDL-FPGA-Verilog] uart_transmitter

[Embeded-SCM Develop] CPLD_UART

[VHDL-FPGA-Verilog] FPGA_VHDL_code

[VHDL-FPGA-Verilog] NIOS_JTAG_UART

[VHDL-FPGA-Verilog] FPGACPLD

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] Actel_Igloo_nano_UART

[VHDL-FPGA-Verilog] UART_FPGA_design

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